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CS51411, CS51412, CS51413, CS51414
Figure 17, and the benefit of the foldback frequency and
current limit is self ? evident.
where:
I S = DC switching current.
When the power switch turns on, the saturation voltage
and conduction current contribute to the power loss of a
non ? ideal switch. The power loss can be quantified as
WSAT +
VO
VIN
IS
VSAT
where:
V SAT = saturation voltage of the power switch which is
shown in Figure 12.
The switching loss occurs when the switch experiences
both high current and voltage during each switch transition.
This regulator has a 30 ns turn ? off time and associated
power loss is equal to
WS + S
I
2
VIN
30 ns
fS
Figure 17. In Short Circuit, the Foldback Current and
Foldback Frequency Limit the Switching Current to
Protect the IC, Inductor and Catch Diode
Thermal Considerations
A calculation of the power dissipation of the IC is always
necessary prior to the adoption of the regulator. The current
drawn by the IC includes quiescent current, predriver
current, and power switch base current. The quiescent
current drives the low power circuits in the IC, which
include comparators, error amplifier and other logic blocks.
Therefore, this current is independent of the switching
current and generates power equal to
WQ + VIN IQ
where:
I Q = quiescent current.
The predriver current is used to turn on/off the power
switch and is approximately equal to 12 mA in worst case.
During steady state operation, the IC draws this current from
the Boost pin when the power switch is on and then receives
The turn ? on time is much shorter and thus turn ? on loss is
not considered here.
The total power dissipated by the IC is sum of all the above
WIC + WQ ) WDRV ) WBASE ) WSAT ) WS
The IC junction temperature can be calculated from the
ambient temperature, IC power dissipation and thermal
resistance of the package. The equation is shown as follows,
TJ + WIC R q JA ) TA
The maximum IC junction temperature shall not exceed
125 ° C to guarantee proper operation and avoid any damages
to the IC.
Using the BIAS Pin
The efficiency savings in using the BIAS pin is most
notable at low load and high input voltage as will be
explained below.
Figure 18 will help to understand the increase in efficiency
when the BIAS pin is used. The circuitry shown is not the
actual implementation, but is useful in the explanation.
it from the V IN pin when the switch is off. The predriver
current always returns to the V SW pin. Since the predriver
current goes out to the regulator ’s output even when the
BIAS
P1
Internal
BIAS
power switch is turned off, a minimum load is required to
prevent overvoltage in light load conditions. If the Boost pin
(VIN * VO ) O )
voltage is equal to V IN + V O when the switch is on, the power
dissipation due to predriver current can be calculated by
V 2
WDRV + 12 mA
VIN
The base current of a bipolar transistor is equal to collector
V in
P2
WBASE + O
current divided by beta of the device. Beta of 60 is used here
to estimate the base current. The Boost pin provides the base
current when the transistor needs to be on.
The power dissipated by the IC due to this current is
V 2   IS
VIN 60
Figure 18.
Internal bias to the IC can be supplied via the V in pin or the
BIAS pin. When the BIAS pin is low, the logic turns P2 on
and current is routed to the internal bias circuitry from the
V in pin. Conversely, when the BIAS pin is high, the logic
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